IBM achieves sub-nanometer chips with nanostack transistors

What happened?

IBM has announced the development of a new chip technology it calls 'sub-1 nanometer chip technology,' although it does not actually reduce the physical dimensions of transistors below 1 nm. Instead, the company has created an architecture called 'nanostack,' which stacks transistors vertically (like a sandwich) to achieve a transistor density close to 100 billion on a chip the size of a fingernail, nearly double that of the previous generation. According to Jay Gambetta, director of IBM Research, this represents 'a significant leap, not just an incremental step.'

The announcement, made in June 2026, builds on years of research in 3D packaging and new transistor architectures. Unlike traditional approaches that shrink transistor size (such as TSMC's 3 nm or 2 nm processes), IBM bets on verticality: instead of making transistors smaller, it stacks them in layers, increasing density without requiring extreme lithography. According to the Ars Technica article, the company claims this architecture can deliver the performance improvements expected from a theoretical chip with sub-nanometer physical features, but without the manufacturing challenges that entails.

Why is this important?

The semiconductor industry faces physical limits in traditional miniaturization (Moore's law). IBM demonstrates that it is possible to continue improving performance without reducing transistor size, opening a path to extend Moore's law through 3D packaging and new architectures. For AI data centers, this translates to greater computing capacity with lower energy consumption, a critical factor given the explosive growth of language models and other intensive workloads.

Historically, Moore's law has driven the industry for decades, but since 7 nm, advances have become more costly and difficult. IBM, which was already a pioneer in 7 nm and 5 nm processes, now proposes a paradigm shift: instead of scaling horizontally, scale vertically. This not only enables higher densities but also reduces the distance signals must travel, improving energy efficiency. In a context where AI data centers consume increasing amounts of energy (estimated to account for 2% of global consumption by 2027), any efficiency improvement has a significant impact.

Consequences for the industry

• Chip manufacturers: TSMC, Samsung, and Intel will need to accelerate their own vertical stacking solutions to keep up. TSMC has already announced its 3D Fabric technology, but IBM claims its nanostack surpasses any current competitor in density. Intel, meanwhile, is developing its Foveros architecture but has not yet reached IBM's figures. The race for 3D packaging is intensifying, and partnerships with manufacturers like Samsung could be key.
• AI companies: They will be able to train larger and more complex models without proportionally increasing energy costs. Companies like OpenAI, Google DeepMind, and Meta, which already operate clusters with tens of thousands of GPUs, will benefit from chips with higher transistor density and lower consumption. Additionally, the technology could enable real-time execution of large language models (LLMs) with lower latency.
• End users: Indirect benefits through more powerful and efficient cloud services. Advances in generative AI, search, and virtual assistants will become faster and more accessible. However, consumers will not see chips with nanostack in their mobile devices in the short term, as IBM focuses on servers and mainframes.

Compared to previous events, such as IBM's announcement of a 7 nm chip in 2015, this new milestone has a more architectural than lithographic focus. In 2015, IBM demonstrated that it was possible to manufacture 7 nm transistors, but commercialization took years. Now, the company is betting on a paradigm shift that could be more disruptive, but also more complex to implement at scale. The first chips based on nanostack are expected to reach IBM Cloud data centers in 2028, although Gambetta did not confirm exact dates.

What should readers know?

This technology is not a real sub-nanometer lithographic process, but an architectural approach that achieves equivalent densities. IBM plans to integrate it into its future chips for servers and mainframes, but there is no commercialization date yet. It is more of an R&D milestone than an immediate product. Moreover, the viability of mass production remains to be proven: vertical stacking of transistors requires precise manufacturing techniques and can increase thermal complexity. IBM claims to have solved these issues with new materials and heat dissipation designs, but details are limited.

In summary, IBM's announcement is a reminder that semiconductor innovation is not limited to shrinking transistor size. 3D packaging and vertical architectures could be key to maintaining the pace of progress in the AI era. However, readers should be cautious: the path from lab to mass production is long and fraught with challenges. As Gambetta noted, 'it's a significant leap,' but it remains to be seen whether the leap lands in the market.

"It's not just an incremental step, it's a significant leap" — Jay Gambetta, IBM Research.

For more details, see the original Ars Technica article (June 2026).