IBM reveals 1 Angstrom process for subnanometer chips

IBM Research has unveiled a subnanometer process technology called 'nanostack,' reaching 0.7 nm (7 Angstroms). In comparison, Intel and TSMC's most advanced nodes for 2028 are 1.4 nm (14 Angstroms). According to Jay Gambetta, director of IBM Research, this breakthrough enables 50% more performance or 70% better energy efficiency compared to the 2 nm node IBM showcased in 2021. Additionally, transistor density reaches nearly 100 billion in an area the size of a fingernail, doubling the density of the 2 nm node. This announcement marks a milestone in the evolution of Moore's Law, which many had declared dead.

Key innovations: 3D stacking and independent contacts

The nanostack architecture stacks n-type and p-type field-effect transistors (FETs) in vertical layers, with a staggered arrangement that allows independent contact to the front and back of each transistor for signal and power. This is achieved through a unique dielectric bonding process that optimizes the channel materials of each layer separately. IBM claims this platform will enable scaling for another decade beyond current nanosheets. Unlike previous approaches, such as Intel's 3D stacking mentioned in 2023 without implementation, or Huawei's LogicFolding architecture that merges two separate wafers, IBM's design introduces vertical staggering that simplifies interconnects. 'Nanostack is not an innovation; it's a device platform that can enable future scaling for another decade beyond the nanosheet,' Gambetta said.

Industry impact and potential applications

IBM no longer manufactures chips, but its nanosheet technology is licensed by major foundries. The company collaborates with Rapidus, a government-backed Japanese foundry, to bring 2 nm manufacturing to Japan. The new process could be applied to CPUs, GPUs, mobile chips, SRAM memory, and AI accelerators. Gambetta highlighted a 40% reduction in SRAM area, crucial for AI chips where cache memory occupies a large portion of the die. This would allow integrating more cores or larger cache in the same space, improving performance in AI workloads. Additionally, energy efficiency is key for data centers, where electricity consumption is a growing operational cost. However, commercial adoption will take at least five years, as the process requires new materials and manufacturing equipment.

What does this mean for the future of computing?

IBM's announcement outlines a roadmap toward 1 Angstrom (0.1 nm) in ten years, implying unimaginable transistor densities today. This would enable chips with trillions of transistors, enabling exascale computing on a single die. However, commercial viability depends on foundries like TSMC, Samsung, or Intel adopting the technology. For now, IBM focuses on transferring knowledge to Rapidus, while competitors like Intel and Huawei explore similar 3D stacking concepts. The race to sustain Moore's Law has intensified, and this breakthrough could define the next decade of microelectronics.

Historical context

Since IBM invented the nanosheet transistor in 2017, the industry has followed that path. Now, with 3D stacking, the limitations of traditional lithography are overcome. This advancement recalls the transition from planar transistors to FinFET (2011), and then to nanosheets (2021); each leap has sustained Moore's Law. Nanostack could be the next major step, comparable to the shift from planar to FinFET in terms of impact. Historically, IBM has pioneered manufacturing technologies, such as the one-transistor DRAM cell in 1966 or the copper interconnect process in 1997. Although IBM sold its manufacturing business to GlobalFoundries in 2014, its research division continues to generate innovations that it later licenses. This model has allowed technologies like nanosheet to be adopted by TSMC and Samsung.

Consequences for businesses and users

For tech companies, the promise of more powerful and efficient chips opens the door to servers with lower energy consumption, mobile devices with longer battery life, and more capable AI accelerators. End users will see performance improvements without increased energy costs. However, mass adoption is not expected before five years, and initial manufacturing costs will be high. Companies relying on high-performance computing, such as AI, cloud, and supercomputing, will be the first to benefit. For example, a data center currently consuming 100 MW could reduce consumption to 30 MW with 0.7 nm chips, or increase computing capacity by 50% while maintaining the same power. For mobile device manufacturers, this means batteries lasting days or laptop-level performance in a phone.

Limitations and challenges

The main challenge is technology transfer to foundries. IBM does not manufacture, so success depends on partners like Rapidus scaling the process. Additionally, competition from Intel and TSMC, which are also working on 3D stacking, could dilute IBM's advantage. Intel has announced its own 3D stacking approach for 2025, albeit with larger nodes (1.8 nm). TSMC, meanwhile, is developing 2D transistors with materials like molybdenum disulfide. Finally, the costs of new materials and processes could delay commercialization. Developing a 0.7 nm node is estimated to require over $10 billion in R&D and equipment. Moreover, integrating materials like germanium or III-V compounds into transistor channels poses manufacturing and reliability challenges.

'This is not just an incremental step; it's a significant leap,' said Jay Gambetta.

In summary, IBM's nanostack represents a remarkable technological advancement that could redefine the semiconductor industry. However, its ultimate success depends on adoption by foundries and overcoming manufacturing challenges. The roadmap toward 1 Angstrom is ambitious but feasible if the pace of innovation continues. Moore's Law, though challenged, remains alive thanks to innovations like this.