IBM unveils chip with 100 billion transistors: Moore's Law extended another decade

What happened?

IBM has announced a prototype chip that integrates about 100 billion transistors in an area similar to a fingernail, doubling the density of its previous 2021 technology. To achieve this, the company adopted an architecture called nanostack, which stacks transistors vertically in two layers, rather than shrinking them horizontally. This design, known as CFET (Complementary Field-Effect Transistor), allows chips to perform up to 50% more work in the same time and be up to 70% more energy efficient, according to IBM. The announcement was made during a press conference on Tuesday, where Jay Gambetta, director of IBM Research, called the breakthrough "a significant leap" and not just an incremental step. Dan Hutcheson, vice president of TechInsights, stated that this innovation "puts another ten or fifteen years on the roadmap."

Why is it important?

Moore's Law, which predicts that the number of transistors on a chip doubles every two years, has been the engine of technological progress for over half a century. However, in the last fifteen years, transistors have reached scales of a few nanometers, where quantum effects interfere with their operation. Vertical stacking offers a way to continue increasing density without reducing transistor size. Historically, the industry has faced similar challenges: in the 2000s, material changes (such as the introduction of high-k dielectrics) allowed miniaturization to continue. Now, vertical stacking represents a comparable paradigm shift. The potential impact is enormous: from more efficient data centers to more powerful processors for artificial intelligence and mobile devices. IBM expects nanostack chips to become widespread in data centers within a decade, helping to better manage energy consumption. According to data from the International Energy Agency, data centers consume about 1% of global electricity, and their demand is growing rapidly with the expansion of AI. A 70% improvement in energy efficiency could significantly reduce this consumption.

How does it work?

The manufacturing process is done layer by layer. First, transistors are built on a silicon layer; then another silicon layer is deposited on top and transistors are fabricated on it; finally, both layers are electrically connected. Unlike other approaches such as AMD's 3D V-Cache or Huawei's LogicFolding, which fabricate the layers separately and then bond them, IBM creates the transistors directly on the bottom layer, allowing for more precise alignment and higher density. Additionally, the transistors on the second layer are not placed directly above those on the first, but are staggered, simplifying wiring and reducing electrical resistance. This staggered design is a key innovation that distinguishes IBM from its competitors. According to Huiming Bu, vice president of global semiconductor R&D at IBM, "monolithic stacking allows for tighter integration and better performance." The CFET architecture combines N-type and P-type transistors in the same vertical structure, optimizing space and energy consumption.

What consequences will it have?

In the short term, IBM will collaborate with semiconductor manufacturers to bring the technology to production. Chip designers are expected to adopt this architecture for CPUs, GPUs, and other processors. In the long term, the technique could extend the life of Moore's Law and maintain the pace of innovation in computing. However, IBM is not the only company in this race: Intel, Samsung, and TSMC are also researching CFETs. Intel has presented its own vision of stacked transistors (called RibbonFET), while TSMC has demonstrated CFET prototypes. IBM's proposal stands out for its staggered design and monolithic approach, which could offer advantages in cost and performance. Nevertheless, the path to commercialization is long: IBM's prototypes typically take years to reach the market. For example, its 7nm technology was announced in 2015 but was not integrated into products until 2018. Moreover, manufacturing stacked chips requires advanced lithographic equipment (such as EUV) and precise layer deposition processes, increasing production costs. For end users, this could translate into faster and more efficient computers, but not immediately. In the business realm, data centers could benefit first, reducing their energy bills and carbon footprint.

What should readers know?

• The chip is a prototype; commercial products could take years to arrive. IBM has been a pioneer in research, but mass production depends on partners like Samsung or GlobalFoundries.
• Energy efficiency is key: up to 70% less consumption for the same workload, which could revolutionize data center sustainability.
• The technology will first be applied in data centers, but could reach consumer devices like smartphones and laptops within the next decade.
• Moore's Law is not dead, but it has changed direction: now it builds upward, not downward. This shift is comparable to the leap from planar transistors to FinFETs in the 2010s.
• Competition is fierce: Intel, TSMC, and Samsung are also advancing in vertical stacking, so IBM is not the only option. IBM's advantage lies in its staggered design and monolithic approach.

"It's not just an incremental step, it's a significant leap," said Jay Gambetta, director of IBM Research.

In summary, IBM's announcement marks a milestone in semiconductor evolution, offering a viable path to continue Moore's Law beyond the physical limits of miniaturization. However, widespread adoption will require overcoming manufacturing and cost challenges, and competition with other tech giants will keep innovation pressure high. The coming years will be crucial to see if this technology becomes the standard of the next decade.